This invention pertains to the field of memory controllers, and more particularly, to a memory controller having a pipelined architecture for controlling access to memory devices in a memory system using an open-page policy, wherein memory pages within a memory device are not closed after each memory access.
Typically, a semiconductor memory system comprises one or more memory devices connected by means of a bus to a memory controller which manages data flow to and from the memory devices. The memory devices may be dynamic random access memory (DRAM) devices, static random access memory (SRAM), etc.
FIG. 1 illustrates the organization of an exemplary memory device 100. The memory device 100 comprises a plurality of memory banks 110. Each memory bank 110 in turn comprises a plurality of memory pages 120 and each memory page 120 comprises a plurality of memory cells 130. The memory pages 120 within each memory bank 110 share a common pair of sense amplifier arrays 140 which are used to sense data stored within the memory cells 130 in the memory bank 110. The total number of memory cells 130 within a memory page 120 is referred to as the xe2x80x9cpage size.xe2x80x9d
The memory cells 130 within each memory page 120 are connected to each other by a word line which has a unique row address within a memory bank 110. Each memory cell 130 in a memory page 120 is connected to a separate bit line, each of which has a unique column address within the memory bank 110. Also, each memory cell 130 in a memory page 120 shares its bit line with corresponding memory cells 130 in all of the other memory pages 120 in the memory bank 110. Thus the memory cells 130 within a memory bank 110 are arranged in a matrix structure of rows and columns. Each memory cell 130 within a memory bank 110 is uniquely addressable by its word line position, or row address, and its bit line position, or column address. Accordingly, each memory cell 130 within a memory device 100 has a unique (memory bank+row+column) address.
Each memory cell 130 stores one bit of data. To access data stored in one or more xe2x80x9ctargetxe2x80x9d memory cells 130 within the memory device 100, the target memory page 120 wherein the target memory cells 130 are located is first xe2x80x9copenedxe2x80x9d by activating the corresponding word line for the target memory page 120. When the word line is activated, the data stored within all of the memory cells 130 connected to the activated word line are transferred via the bit lines to the sense amplifier array 140. From the sense amplifier array 140, the data from one or more target memory cells may be read from memory device 100 and communicated via the memory bus. After the memory access request is completed, each sense amplifier within the open target memory page 120 is then xe2x80x9cprechargedxe2x80x9d to prepare the sense amplifier for a subsequent operation. This operation is said to xe2x80x9cclosexe2x80x9d the target memory page 120.
As processor speeds increase, there exists a need for memory systems having faster and faster memory access speeds and data throughputs. Therefore high performance memory systems with new architectures are being implemented. One such architecture is the Direct Rambus(trademark) memory architecture. A memory system according to the Direct Rambus(trademark) memory architecture uses a narrow memory bus comprising a few signal channels (e.g., 30) connected device-to-device and operating at a very high clock rate to communicate memory access requests and data between a memory controller and one or more memory devices.
FIG. 2 shows such a memory system 200 wherein a plurality of memory devices 210 are connected to a memory controller 230 via a narrow, high-speed memory bus 220. The memory bus 220 comprises a small number of very high speed signal channels which carry address, data and memory access control information between the memory controller 230 and the memory devices 210. The memory system 200 uses a packetized signaling technology for the signal channels in the memory bus 220. The memory system 200 provides several advantages over traditional memory architectures, including a substantially reduced number of pins on the memory controller 230 and memory devices 210, and a higher sustained bandwidth for the memory bus 220.
A processor connected to the memory system 200 may access data stored in a target memory device 210 by communicating a memory access request to the memory controller 230. Within the memory system 200, memory access is effectuated by means of control packets communicated from the memory controller 230 to the target memory device 210, via one or more control signal channels in the memory bus 220. Data is communicated from the target memory device 210 by means of separate data packets communicated from the target memory device 210 via a separate data signal channel in the memory bus 220.
Within the memory system 200, control packets communicate control commands, including memory access commands (e.g., Activate, Precharge, Read, and Write commands) and memory maintenance commands (e.g. Refresh, and Power Down commands), from the memory controller 230 to a memory device 210. The control packets have predefined fields for control command type, memory address, and the like and are divided into row control packets and column control packets. Row control packets are communicated via a row control signal channel in the memory bus 220. Among other things, row control packets are used: to issue Activate commands to activate a word line and thereby to open a memory page within a memory device 210; to issue Precharge commands to precharge memory cells in an open memory page, and thereby close the open memory page, within a memory device 210; and to issue Refresh commands to refresh the data contents stored in memory cells within a memory device 210. Column control packets are communicated via a column control signal channel in the memory bus 220. Among other things, column control packets are used to issue Read commands and Write commands to one or more memory cells within the memory device 210.
The operations of opening and closing a memory page to access data stored within a memory device 210 require time for the associated control commands to be communicated via the memory bus 220, and require some time to be performed by the memory device 210. While a memory page is being opened or closed, the memory device 210 cannot provide data from memory cells in that memory page, or any other memory page, within its memory bank. Accordingly, the opening and closing operations consume bandwidth and can reduce the data throughput of the memory system 200.
In general, a memory system can implement either a xe2x80x9cclose-pagexe2x80x9d policy, where after each memory access request to memory cells in a memory page in a memory device, the corresponding random memory page is closed, or an xe2x80x9copen-pagexe2x80x9d policy, where the memory page is left open after a memory access request, until some other event necessitates closing it (e.g., a memory access request to another memory page within the memory bank).
xe2x80x9cLocalityxe2x80x9d refers to the degree to which consecutive memory access requests are addressed to a same memory page within a memory system. The application(s) being performed by a processor issuing memory access requests to a memory system typically determine the degree of locality in memory access requests. In turn, the degree of locality in memory access requests in the memory system determines whether it is better to implement an open-page policy or a close-page policy.
If the pattern of memory access requests have a low degree of locality then it is preferable to use a close-page policy. In that case, every memory access ends with all memory pages and memory banks closed and there is no need to check whether a memory page or memory bank is open or closed before executing the next memory access request.
However, for certain other applications, where there is a high degree of locality in memory access patterns, it is preferable to use a memory system having an open-page policy, which leaves a memory page open after a memory access, and only closes it later when some subsequent event necessitates it. In that case, if a memory access request is addressed to the same memory page as the previous memory access request, the precharge operation for the first memory access request, and the activation operation for the second memory access request, can each be avoided. This increases the data throughput in the memory system.
The memory system described herein operates according to an open-page policy. As such, the memory system imposes a number of constraints which must be adhered to by the memory controller in generating and issuing control commands in response to memory access requests received from a processor. These constraints include logical constraints, timing constraints, and physical constraints which are each discussed in detail below.
As discussed above, a memory device may be partitioned into a number of memory banks. FIG. 3 shows an arrangement of memory banks 310 in a memory device 210 which may be used in the memory system.
In the memory device 210, adjacent memory banks 310 share a common sense amplifier array 320. This allows the memory device 210 to have more memory banks 310 within the same or similar die area. Since only one memory page within a memory bank 310 may be open at any given time, increasing the number of memory banks 310, reduces the number of memory page conflicts within the memory device, leading to higher performance, and also reducing the power consumed by the memory device.
At any time, a memory bank can have one of three logical memory bank states: closed, open, or locked.
A memory bank is closed when neither of its associated sense amplifier arrays contain the data from either the memory bank itself, or an adjacent memory bank sharing a sense amplifier array. Before data may be accessed from a closed memory bank, it must first be opened, together with a desired memory page, by an Activate command from the memory controller.
A memory bank is opened when data from memory cells in an open memory page have been transferred to one of its sense amplifier arrays by a previous Activate command. When a memory bank is open, the memory controller can access data from the memory cells in the open memory page. However, if the memory controller wants to access data from another (closed) memory page within the open memory bank, the open memory bank must first be closed. The open memory bank is closed by the memory controller issuing a Precharge command addressed to the open memory page. Then, the memory bank is xe2x80x9creopenedxe2x80x9d to the desired memory page by a subsequent Activate command from the memory controller.
When a memory bank is open, its adjacent memory banks are unavailable because their common sense amplifier array is being used by the open memory bank 310. FIG. 3 illustrates one example of memory banks 310 (indicated by a xe2x80xa2) which can simultaneously be open within the memory device 210. Memory banks which are unavailable due to their common sense amplifier array being used by one or both adjacent open memory bank are said to be in a xe2x80x9clockedxe2x80x9d state. When it is desired to access data from a locked memory bank, the adjacent open memory bank(s) must first be closed to free up the shared sense amplifier array(s). This action places the locked memory bank in a closed state. Once closed, the memory bank may be opened, together with a desired memory page to access data.
From the above description, it can be seen that a memory system comprising one or more memory devices with memory banks sharing common sense amplifier arrays impose a number of logical constraints upon a memory controller issuing control commands to the memory device(s). That is, when issuing a control command to one or more target memory cells in a target memory bank, the memory controller must insure that the target memory bank has a memory bank state suitable to receive the control command. For example, a closed or locked target memory bank cannot properly receive and process a read command. The target memory bank must first be opened. Also, a read command may be issued to a target memory bank only after the target memory bank has been activated by an Activate command. As another ready example, the memory controller should issue a Precharge command to a memory bank only if the memory bank has been previously activated. Many such logical constraints exist.
As noted above, each control command requires some amount of time to be communicated via the memory bus, and the memory device requires some amount of time to execute each received control command. FIGS. 4A through 4F illustrate certain timing constraints or requirements for the memory system which must be satisfied by control commands issued by a memory controller.
FIG. 4A shows a xe2x80x9ctransaction pipelinexe2x80x9d for control packets and data packets communicated via the memory bus to effectuate a memory access request in the memory system. The transaction pipeline comprises: row control packets communicated via a row control signal channel; column control packets communicated via a column control signal channel; and data packets communicated via a data signal channel, all separated in time.
FIG. 4B shows the transaction pipeline for a read transaction which effectuates a read memory access request received by the memory controller from a processor, for example. In this particular case, the memory controller issues a row control packet comprising an Activate command, followed by one or more column control packets comprising a Read memory access request. Data then appears on the data signal channel in the memory bus some y cycles (e.g., eight cycles) later. Wherever possible, the memory controller uses unoccupied time on the control signal channels to issue further control commands to effectuate other memory access requests and operations, thereby increasing data throughput.
FIG. 4C shows the transaction pipeline for a write transaction effectuating a Write memory access request. The write transaction is similar to the read transaction shown in FIG. 4B, except that in the case of a write transaction, the data packet(s) appears on the data signal channel in the memory bus z cycles (e.g., six cycles) after the column control packet, rather than y cycles as in the read transaction.
FIG. 4D shows the transaction pipeline for read transactions. The control packets should be pipelined as tightly as possible to increase data throughput on the data signal channel of the memory bus. Write-write transactions differ from read-read transactions only in the time interval between when the control packets are communicated and when the data packets appear on the data signal channel in the memory bus. The data packets appear on the data signal channel z cycles after the write control packet in a write-write transaction, versus y cycles in the case of a read-read operation.
FIG. 4E shows the transaction pipeline for back to back read-write transactions. Due to timing differences on the memory bus between read and write transactions, a gap of |zxe2x88x92y| packets must be provided by the memory controller between the column control packets in order for the two transactions to produce full utilization of the data signal channel in the memory bus.
FIG. 4F shows the transaction pipeline for back to back write-read transactions. In this case, the column control packets can be tightly packed, however this results in a gap appearing between data packets on the data signal channel due to timing differences between the write and read transactions.
Inspection of FIGS. 4A-4F shows that the memory system imposes timing constraints upon control packets issued by a memory controller. Each control command requires a certain amount of time to be communicated to and executed by a target memory device. For proper operation, a control command should only be issued when the target memory device is known to be in a state suitable to receive this control command, and only after the memory device has completed all previous control commands which may affect the proper execution of the present control command.
For example, when a memory device receives an Activate command for a particular memory page in a memory bank, the memory device requires a minimum time period (e.g., 20 nsec.) to activate the memory bank before the memory device can properly process a subsequent Read control command directed to the same memory bank. Similarly, when a memory device receives a Precharge command to precharge a memory page in a memory bank, it requires a minimum period of time to perform the precharge operation before it can properly receive and process another precharge operation for a different memory page in the same memory device. Therefore, the memory controller must insure that it coordinates the timing of all control commands which it issues to insure that they can be properly processed by the target memory device.
As discussed above, the memory system operates according to a packetized protocol with control packets and data packets. The memory bus thus comprises a column control signal channel for communicating column control packets, a row control signal channel for communicating row control packets, and a data signal channel for communicating data packets. These signal channels each have an associated set of physical pins on the memory controller and memory devices. Other pins on these devices are used for clock signals, initialization signals, and power/ground. Each control command occupies a set of signal channels and associated physical pins for a certain period of time. The memory controller may not issue another control command which would use the same signal channel and physical pins during the same time period.
The control and data signal channels also have interdependencies wherein when a control command is issued on a control signal channel, physical pins associated with the data signal channel are then occupied for a specified period of time. For example, after a Read command is issued by a memory controller to a target memory device, the target memory device drives the data signal channel, and occupies the associated physical pins, for a specified period of time.
This is but one example of many physical constraints that are imposed on memory controller operation by the memory bus and related resources.
Accordingly, it would be advantageous to provide a memory controller for use in a high performance memory system which issues control commands satisfying logical constraints, timing constraints, and physical constraints for the memory system. It would also be advantageous to provide a memory controller well suited to processing applications with a high degree of locality in memory access patterns.
The present invention comprises a pipelined memory controller for a high performance memory system.
In one aspect of the invention, a pipelined memory controller checks and resolves all logical, timing and physical constraints on a memory access command before issuing the command. The pipelined memory controller isolates and resolves logical, timing, and physical constraint checks separately in two pipelined stages.
In another aspect of the invention, a pipelined memory controller controls memory access to memory devices in a memory system with a parallelized memory bus having a small number of very high speed signal channels which carry address, data and control information between the pipelined memory controller and the memory devices. Preferably, the memory system uses a packetized signaling technology for the signal channels in the memory bus.
In yet another aspect of the invention, a pipelined memory controller implements an open-page policy which improves memory access efficiency for applications with a high degree of memory access locality.